The present invention relates to a method of manufacturing semiconductor devices with sub-micron dimensions. The present invention has particular applicability in manufacturing high density semiconductor devices with transistors having reduced short-channel effects and improved silicide contact resistance.
The increasing demand for micro-miniaturization requires scaling down various horizontal and vertical dimensions in various device structures. As the depth of the ion implanted source/drain junctions of transistors is scaled down, there is a corresponding scaled increase in the substrate channel doping in order to maintain a constant electric field in the transistor channel for higher speed performance. These objectives are achieved, in part, by not only forming shallow junctions but also forming source/drain extensions with an abrupt junction/dopant profile slope in proximity to the transistor channel in order to reduce penetration of the source/drain dopant into the transistor channel which occurs as the junction/profile slope becomes less abrupt. Such short channel effects result in poor threshold voltage roll-off characteristics for sub-micron devices.
The demand for micro-miniaturization also requires reduced contact silicide contact resistance. This objective can be achieved by forming a uniformly high dopant concentration at the upper surface of the substrate. However, it is very difficult to provide a uniform high dopant concentration at the upper surface of the substrate.
There exists a continuing need for methodology enabling the fabrication of semiconductor devices containing transistors with accurately defined source/drain extensions and source/drain regions with a uniformly high dopant concentration at the upper surface of the substrate.
An advantage of the present invention is a method of manufacturing a semiconductor device having reduced short-channel effects.
Another advantage of the present invention is a method of manufacturing a semiconductor device having scaled MOSFETs with reduced silicide contact resistance.
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method manufacturing a semiconductor device, the method comprising: forming a gate electrode, having an upper surface and side surfaces, over an upper surface of a substrate with a gate insulating layer therebetween; forming first sidewall spacers on the side surfaces of the gate electrode; ion implanting to form deep pre-amorphized regions extending into the substrate defining future deep source/drain regions; ion implanting an impurity into the deep pre-amorphized regions forming deep source/drain implants; laser thermal annealing to recrystallize the deep pre-amorphized regions and activate the deep source/drain regions; removing the first sidewall spacers; ion implanting to form shallow pre-amorphized regions on each side of the gate electrode extending into the substrate defining future shallow source/drain extensions; ion implanting an impurity into the shallow pre-amorphized region; and laser thermal annealing to recrystallize the shallow pre-amorphized regions and activate the shallow source/drain extensions.
Embodiments include forming second sidewall spacers on the gate electrode after activating the shallow source/drain extensions and forming metal silicide layers on the upper surface of the gate electrode and on the upper surface of the semiconductor substrate overlying the deep source/drain regions. Further embodiments of the present invention comprise forming an oxide liner on the side surfaces of the gate electrode and a portion of the upper surface of the substrate and forming silicon nitride sidewall spacers as both the first and second sidewall spacers.
Additional advantages of the present invention will be readily apparent to those skilled in the art from the following detailed description wherein the embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carry out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, not as restrictive.